ASIC Engineer || RTL Design, Verilog, System Verilog || CDC, Lint || Exp - 4 to 7 years

About the role

ASIC Engineer || RTL Design, Verilog, System Verilog || CDC, Lint || Exp - 4 to 7 years Bangalore, India Bangalore India

Key responsibilities

• check_circleCollaborate with the team on day-to-day project tasks
• check_circleLearn tools and processes used by the organization
• check_circleDocument work and participate in team meetings
• check_circleSupport quality checks and continuous improvement

Requirements

• check_circleRelevant education or self-taught skills for the role
• check_circleStrong willingness to learn and take feedback
• check_circleGood communication in English (written and verbal)
• check_circleAbility to commit to the internship/role duration

Skills & keywords

Benefits & perks

• check_circleMentorship
• check_circleCertificate of completion
• check_circleFlexible work arrangement where applicable